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| BCM5632E (R) 12 GIGABIT + 1 10-GIGABIT SWITCHING PROCESSOR FEATURES * Supports 12 Gigabit ports and one 10-Gigabit uplink in wirespeed operation * Gigabit ports support TBI (1000BASE-X) or GMII (1000BASE-T) interfaces * Uplink supports XGMII interface for 10-Gigabit SUMMARY OF BENEFITS * Complete switch on a chip integrates 12 10/100/1000 and one * L2 search table supports 32K MAC addresses * Jumbo Frame support (9 Kbyte) * Supports full 4K VLAN addresses and 802.1s Multiple Spanning Tree protocol * * * * * Supports 802.1p and/or DiffServ with four priority queues * Supports 802.3ad link aggregation control protocol (LACP) and marker protocol * Supports selected MIB groups in RMON and SMON * Supports up to 32K IP multicast groups with the option to cross VLAN boundaries 10G Ethernet Media Access Controllers (MACs) supporting RMII, GMII, XGMII and TBI interfaces, including multilayer forwarding and filtering logic and internal ARL tables and packet buffering. Supports 32K internal MAC addresses, which are shared by all ports. Multicast MAC addresses, including IP multicast, can also be stored and searched. Supports Quality of Service (QoS). Each output port has four priority queues and their assignment can be based on DiffServ TOS field or the 802.1p priority field. Filters and forwards traffic at full wirespeed on all 13 ports at all layers of functionality. This equates to 44 Gbps of bandwidth. Provides a mechanism to bundle together up to 12 ports at the same speed to form a port bundle or a trunk group, establishing up to six trunk ports. * Full-duplex and half-duplex operation with IEEE 802.3x flow control and backpressure * Built in 32-bit, 33-MHz PCI bus interface * Flexible multiplexer modes * Packaged in an 841-pin or a 785-pin BGA BCM5632E Switching Solution Fiber XCVR or BCM5464 GMII/TBI GMII/TBI Fiber XCVR or BCM5464 GMII/TBI GMII/TBI Fiber XCVR or BCM5464 GMII/TBI GMII/TBI Fiber XCVR XAUI BCM8011 XGMII BCM5632E PCI CPU Subsystem System Bus OVERVIEW Output Queueing Shared Buffer Buffer Manager MIB Counters PCI Interface To CPU Rx FIFO Tx FIFO Serial to Parallel Parallel to Serial Table Maintenance Port Manager L2 MAC Table Rx FIFO Rx FIFO Rx FIFO Tx FIFO Tx FIFO 10 G MAC 10 G-Port The BCM5632E switching processor chip supports 12 Gigabit ports and one 10-Gigabit uplink with all ports in wirespeed operation. The BCM5632E is ideal for applications such as multi-Gigabit port switches or aggregating multiple-Gigabit ports to a 10-Gigabit backplane. For Gigabit ports, the BCM5632E supports PCS (802.3z, 1000BASE-X) or GMII (802.3ab, 1000BASE-T) interfaces with full-duplex operation at Gigabit speed, and full- or half-duplex operation at 10/100 Mbps speed (using 1000BASE-T). For the uplink port, the BCM5632E supports XGMII. The BCM5632E supports 802.1Q VLAN tagging as an option (Qon). The BCM5632E supports 802.1v VLAN Classification by Protocol. There are four user-programmable protocols that can be set up per port by the VLAN Classification EtherType and the VLAN Priority/TAG registers. The BCM5632E supports 32K internal MAC addresses which are shared by all ports. Multicast MAC addresses including IP multicast can also be stored and searched. The BCM5632E also supports 4K VLAN addresses with the 802.1s Multiple Spanning Tree option, and flexible and programmable ingress and egress checking rules for VLAN processing. Broadcom(R), the pulse logo, and Connecting everything(R) are trademarks of Broadcom Corporation and/ or its subsidiaries in the United States and certain other countries. All other trademarks mentioned are the property of their respective owners. BROADCOM CORPORATION 16215 Alton Parkway, P.O. Box 57013 Irvine, California 92619-7013 (c) 2004 by BROADCOM CORPORATION. All rights reserved. 5632E-PB01-R 07/08/04 Tx FIFO G MAC G MAC VLAN Table G-Port G-Port The BCM5632E also supports 802.3ad port aggregation. The 12-Gigabit ports can form up to six trunks, with a maximum of twelve ports in a trunk. The distribution algorithm is user-selectable. The Link Aggregation Control Protocol (LACP) frames are handled by the accompanying CPU and the marker protocol is handled in hardware. The BCM5632E can be initialized and configured by an EEPROM or a CPU, which is also responsible for search table updates and management functions. The CPU is a separate port to the device, containing its own Tx FIFO and Rx FIFO. The device implements a 32-bit, 33-MHz Peripheral Component Interconnect (PCI) for flexible CPU selection and interface. Other features include frame trapping and forwarding to the CPU, port monitoring, and broadcast storm control to reduce broadcast traffic through the switch. The BCM5632E also offers a flexible multiplexer mode in which the L2 switching functionality can be turned on and off on a per-port basis. (R) Phone: 949-450-8700 Fax: 949-450-8710 E-mail: info@broadcom.com Web: www.broadcom.com |
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